RISC-V Summit Europe is coming to Bologna, Italy, with a program that reflects just how far the ecosystem has come since we gathered in Paris a year ago. Taking place June 8–12 2026 at the Palazzo dei Congressi, the summit unites members, manufacturers, researchers, public institutions, academics and students, all helping to nurture the RISC-V open standard instruction set architecture (ISA).

There is something very fitting about the RISC-V ecosystem gathering in Bologna. The city’s university, the oldest in the Western world, was founded in 1088 by students who wanted to take their education into their own hands. Over 900 years later, that same instinct surfaced at University of California Berkeley, where students and staff created RISC-V in 2010: an ISA deliberately designed to put the ability to learn and build silicon chips into anyone’s hands.

Yet Bologna is no incidental host. The University of Bologna (‘Unibo’) has been at the heart of European RISC-V research for over a decade, through the long-running PULP RISC-V research platform. It’s also a key partner in TRISTAN, the EU Chips Joint Undertaking-funded initiative to expand and industrialize the European RISC-V ecosystem.

An engaging schedule of speaker sessions and workshops

The core summit runs from Tuesday, June 9 to Thursday, June 11, with Monday activities focused on our Intro to RISC-V and new developer workshops, as well as working group meetings. Plenary sessions begin on Tuesday morning at 9am.

The conference program will help attendees explore both commercial and research applications of RISC-V, with sessions spanning embedded systems, AI, automotive, high-performance computing, security, space, software enablement and open hardware research. In particular, the recent arrival of silicon compliant with the RVA23 hardware profile will undoubtedly shape many of this year’s keynotes, demos and show floor conversations.

While the number of exciting sessions is far too many to detail here, some of our expected highlights include:

Open-Source Microprocessors in the Internet of Trees

One of our favorite use cases of edge ML in recent years saw devices deployed throughout the rainforest to listen to the sound of chainsaws, denoting illegal logging activity. This session explores how RISC-V is now being used to take this ‘Internet of Trees’ concept further; deploying ultra-low-power, secure, and custom processors throughout forests to turn them into intelligent, real-time sensing networks for monitoring biodiversity, climate, and environmental change. It’ll be delivered by Marcello Zuffo and Laisa-USP Caroline Costa de Biase of the University of São Paulo.

RISC-V for Low-Power AI in Next-Generation Smart Glasses

Marco Fariselli of Italian eyewear corporation Luxottica will examine one of the toughest engineering balancing acts in consumer hardware: delivering advanced AI features in smart glasses without reducing battery life or wearability. We look forward to hearing how RISC-V’s adaptability is finally opening the door for product-driven companies to build highly specialized silicon that’s light enough that the wearer forgets it’s there.

RISC-V: Enabling Open Physical AI

Luca Benini is Professor at the University of Bologna, Chair of Digital Circuits and Systems at ETH Zurich, and leads PULP. He’ll be delivering a keynote on Enabling Open Physical AI (being AI systems that perceive, reason about, and interact with the real world, rather than existing solely in software). Benini promises concrete examples of how RISC-V enables deep domain specialization for energy efficient, safe and robust Physical AI systems, from robots to cars to satellites.

Matrix Extensions for RISC-V: Delivering on the Promise

Matrix multiplication is fundamental to many AI workloads, and work has been ongoing for several years now to define how to standardize matrix compute capability within the RISC-V architecture. At Summit Europe in Paris last year, this effort was restructured into multiple complementary approaches, in recognition that the breadth of the RISC-V ecosystem requires a family of solutions rather than one rigid standard. In Bologna, VRULL GmbH’s Philipp Tomsich will deliver the first significant report on progress across the matrix extension family, as two of the extensions – the Integrated Matrix Extension (IME) and the Vector Matrix Extension (VME) – converge on specification freeze, with compiler unification work underway to give AI frameworks a single path covering both. A great opportunity to get up to speed on matrix just before it lands.

Beyond Privilege: The RISC‑V Isolation Toolbox from Microcontrollers to Confidential Computing

The philosophy of complementary approaches rather than a single rigid standard isn’t unique to matrix extensions: it runs just as deeply through RISC-V’s approach to security. Rather than treating isolation as a mechanism bolted on at the end, the community has built a layered toolbox of complementary techniques that can be combined differently depending on the threat model and the hardware. Andrew Dellow of Qualcomm will walk us through that toolbox in Bologna: from physical memory protection in microcontrollers, through virtualization and hardware-enforced compartmentalization, up to Supervisor Domains – an emerging architectural direction that pushes isolation further still. A session of enormous relevance that belongs on every attendee’s list.

On the show floor, attendees will discover the latest technical demonstrations from RISC-V members, while our Developer Zone showcases a selection of RISC-V hardware, from $5 embedded boards to AI powerhouses and complex FPGA devices. You’ll also find posters, academic demos, developer workshops, technical working group meetings and thematic sessions, including RISC-V in Space and TRISTAN.

Empowered by our sponsors

RISC-V Summit Europe 2026 is organized by RISC-V International, the University of Bologna and Planning. Platinum sponsors include BOSC, E4 Computing, Next Silicon, Nuclei Systems and MIPS. Gold sponsors include Breker Systems, CEA, Epic Semi, ESWIN Computing, SiFive, Tenstorrent, Tristan+Isolde and XUANTIE. Silver sponsors include Akeana, Andes, Arteris, Baya Systems, Barcelona Supercomputing Center, Chips-IT, CircuitSutra, GLIWA, Lauterbach, Microchip Technology, OmniTrust, PlanV, Pulp Platform, Real Intent, RISE, SEGGER, SpacemiT and Tera Pines.

Online registration is open until Friday, June 5th, with on-site registration available at the Summit venue after that date. Registration includes access to the core summit from Tuesday, June 9 to Thursday, June 11, including plenaries, poster sessions, demo theater, the evening events and the exhibition area.

_The RISC-V Summit is a community-curated content, research and innovation driving the next wave of growth for RISC-V._

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